A negative voltage level shifter is a circuit that shifts a logic level signal to a negative voltage level. Negative voltage level shifters are basic building blocks in all non-volatile memories, which require high positive and negative voltages for their program and erase operations.
FIG. 1 shows a basic conventional negative level shifter circuit 100. The circuit 100 uses 8 transistors (4 p-type metal-oxide-semiconductor (PMOS) transistors and 4 n-type metal-oxide-semiconductor (NMOS) transistors) and one inverter 102. PMOS transistors MP3 and MP4 act as one cascode stage where their gates are driven by a supply voltage named GCASC. Similarly, NMOS transistors MN1 and MN2 act as another cascode stage, and their gates are also driven by the supply voltage GCASC. The circuit 100 uses three supply signals, namely VDD, VNEG and GCASC. Input signals IN and IN_N are typically of VDD voltage level. There are four output signals OUTH, OUTHN, OUT and OUTN, which can vary from VDD to VNEG depending upon the input signal. Table 1 shows the truth table for the negative level shifter circuit 100.
TABLE 1INPUTOUTPUTINOUTOUTNOUTHOUTHN0VNEGGCASC-VNEGVDDVtnVDDVCASC-VtnVNEGVDDVNEG
where Vtn is the threshold voltage of the NMOS transistors.
However, in circuit 100, outputs OUT and OUTN are taken from the nodes which are not very well driven. As shown in Table 1, output signals OUT and OUTN may each vary from GCASC-Vtn to VNEG. That is, some outputs of the circuit are dependent on the threshold voltage Vtn of the NMOS transistors. If there is any variation in threshold voltage Vtn, the output level also changes accordingly.
Also, when a user drives a capacitive load from outputs OUT and OUTN of circuit 100, the circuit may become very slow. This is because these nodes are not very well driven and any extra capacitance can slow down the circuit behaviour. This problem becomes more severe when the supply voltage VNEG is more negative (e.g. more than safe operating area (SOA) limit of transistors).
To address the issue of varying voltage levels, in an existing approach, cross-coupled PMOS transistors are added to the circuit. FIG. 2 shows a common negative level shifter circuit 200 according to a prior art approach. The circuit 200 uses 10 transistors (6 PMOS transistors and 4 NMOS transistors) and one inverter 202. PMOS transistors MP1 and MP2 are used as the input transistors. PMOS transistors MP3 and MP4 are used as one cascode stage which prevents the path between supplies VDD and VNEG. Similarly, NMOS transistors MN1 and MN2 are used as another cascode stage which prevents the direct path between VDD and negative voltage VNEG. Transistors MN3 and MN4 are used as cross-coupled NMOS logic, which depending upon the input signal, decides the output voltages and locks the state. Another cross-coupled pair is made using PMOS transistors MP5 and MP6. This pair forces the output nodes OUT and OUTN to full GCASC level and locks the state. The circuit 200 also uses three supply voltages, namely VDD, VNEG and GCASC. Input signals IN and IN_N are of VDD voltage level. There are four output signals OUTH, OUTHN, OUT and OUTN, which may vary from VDD to VNEG depending upon the input signal. Table 2 shows the truth table for the negative level shifter circuit 200.
TABLE 2INPUTOUTPUTINOUTOUTNOUTHOUTHN0VNEGGCASCVNEGVDDVDDVCASCVNEGVDDVNEG
However, in the circuit 200, the cross-coupled PMOS transistors add a more critical issue. For example, if the input signal IN changes from “0” to VDD, the inverted input signal IN_N changes from VDD to “0” which, in turn, pulls up the output OUTH to VDD via PMOS transistors MP2 and MP4. As output OUTH is charged to VDD and similarly output OUTHN is discharged to the threshold voltage Vtp of the PMOS transistors, according to the cross-coupled action (at NMOS transistors MN3 and MN4), output OUT should be charged to “GCASC-Vtn” (which has earlier been discharged to VNEG). Once output OUT node charges to “GCASC-Vtn”, it discharges the output node OUTN to VNEG and eventually PMOS transistors MP5 and MP6 locks the output nodes OUT and OUTN to GCASC and VNEG. However, if output nodes OUT and OUTN do not get charged or discharged to the right direction (which can be possible because of reasons such as heavy load capacitance, unbalanced capacitive load at OUT and OUTN nodes, i.e. one of the nodes drives more capacitance than the other, etc.), the PMOS transistors can lock the output nodes at the wrong voltage level, which can cause a static current path in the circuit and eventually a functionality failure. This problem is more prominent in circuits with more negative supplies.
In another example, suppose IN=“0” which forces IN_N=“VDD”, then user expects output node OUT to be at VNEG voltage level and output node OUTN at GCASC voltage level; and similarly, output node OUTH at VNEG and output node OUTHN at VDD voltage levels, respectively. However, because of unbalanced load capacitance, output OUTN tries to be locked at VNEG voltage (rather than GCASC). For this locking system, PMOS transistors MP5 and MP6 are triggered. As output OUTN goes more than the “GCASC” voltage level, a current path forms from VDD to VNEG via transistors MP1, MP3, MN1 and MN3. This current path drops the VDD voltage level or moves VNEG voltage level slightly positive. This change in voltage levels can eventually cause the functionality failure.
Another issue with cross-coupled PMOS transistor pair (here MP5 and MP6) is that there is a junction voltage stress across the bulk and drain junctions, as the bulk junctions of these PMOS transistors can be biased at supply voltage “VDD” or minimum at “Ground” level. The sources of both PMOS are connected at GCASC voltage and the drains of both transistors can go up to VNEG voltage level. Thus, whenever the drain of any PMOS transistor is at VNEG voltage level, there is a bulk-to drain-junction voltage stress. This stress typically increases with more negative values of VNEG voltage. This stress can cause a reliability issue in the circuit.
Further, these PMOS transistors are typically made very weak because their strength affects the size of the cross-coupled NMOS pair (MN3 and MN4). On the other hand, if their size is made small, it will slow down the circuit response. This can be slower for high capacitive load.
FIG. 3 shows a multi-stage, here a two-stage, negative level shifter circuit 300 according to another prior art approach. In this circuit 300, the 1st stage is made using inverter 302 and 4 transistors. PMOS transistors MP1 and MP2 act as the input pass transistors and NMOS transistors MN1 and MN2 are used as a cross-coupled pair. The supply to 1st stage is chosen in such a way that none of the transistors is in a stress condition. Two output signals are taken from 1st stage, namely OUT1 and OUTN1, and are provided as inputs of the 2nd stage which comprises two PMOS transistors MP3 and MP4, and cross-coupled NMOS transistors MN3 and MN4. The supply to the 2nd stage is chosen depending on several criteria. For example, none of the transistors should be in stress condition; supply NEG2 should be less than (i.e. more negative) supply NEG1, e.g. by at least (Vtp+margin), so that output signals OUT1 and OUTN1 are able to pass and block supply NEG2; if the level of shift of supply VNEG is still not obtained, a 3rd stage should be added and the outputs of 2nd stage become the inputs of 3rd stage. Table 3 shows the truth table of two-stage negative level shifter circuit 300.
TABLE 3INPUTOUTPUTINOUT1OUTN1OUT2OUTN20NEG1VDDVNEGNEG2VDDVDDNEG1NEG2VNEG
The circuit 300 can be used for a high negative voltage level shifter. However, a main issue with this approach is that the complete circuit has to be broken down into multiple stages (until the exact voltage level shift is achieved), and for each stage different voltages are needed. For example, if the circuit is broken down into two stages then at least 4 supply voltages are required. If a more negative voltage is desired, the number of stages may increase. On the other hand, it is typically very difficult to provide these multiple supplies on any of the system on a chip (SOC). Another issue with this approach is that an output signal continuously varying between VDD and VNEG is typically not obtained. Rather, output signals are available in different segments, e.g. between VDD and NEG1 or between NEG2 and VNEG.
A need therefore exists to provide a negative voltage level shifter circuit that seeks to address at least one of the above problems.